calibre hcell file format

 ***** calibre hcell file format *****
i.e.
//layout name    || cdl source name
ABC          DEF        //one to many
ABC          GHI        //one to many
UVW          XYZ        //many to one
RST          XYZ        //many to one
LMN          PQK        //one to one
JFQ          KPT        //one to one

output a shape/net to gds format

 ***** output a shape/net to gds format *****
DRC CHECK MAP "rule_check" GDSII "layer number" "datatype" "filename"
i.e.
Grow_Metal1 { @ Grow metal1 by 0.1u
        SIZE metal1 BY 0.1
    }
DRC CHECK MAP Grow_Metal1 GDSII 21 0 "./mask/grown_m1.gds"

i.e.
LAYER metal metal1 metal2 metal3 // define layer set "metal"
Plot_RESET { @ Output all metal shapes beloging to RESET net
        NET metal RESET
    }
DRC CHECK MAP Plot_RESET GDSII 1 0 "./plots/RESET.gds"

To probe signal from layout for reviewing

This can be done by running DRC check
Keep the layer and connection definition, delete the rule checks in the rule deck (NOT the header file),
then add the following commands at end of the rule deck:

*** remember to set "DRC MAXIMUM RESULTS ALL", since the result output

*** may be exceed the max. limits

// probe nets
Plot_VDDA { @output all metal shapes belonging to VDDA net
NET Metaltop VDDA
NET Met3 VDDA
NET Met2 VDDA
NET PolyxRes VDDA
NET Nsd VDDA
NET Psd VDDA
}
DRC CHECK MAP Plot_VDDA GDSII 6 0 "./plots/VDDA.gds"

Convert verilog netlist to spice netlist

"v2lvs" (come along with Calibre) can convert verilog netlist to Calibre format netlist for LVS purpose

       v2lvs -v verilog_in.v -o spice_out.sp -w 3


for more complex syntax put into a script, say "v2sp.sh"

      v2lvs -n -s0 GND -s1 VDD -s inc_1.cdl -s inc_2.sp -lsp sp_ref_lib.sp -v $1 -o $2

e.g. run in console:
./v2sp.sh input.v output.sp


##
-n :  make the unconnected pins to get numbered connections starting at 1000
-s0 : default global ground is changed to
-s1 : default global power is changed to
-s : causes the string .INCLUDE "filename" to be put at the beginning of the generated spice file
-lsp : Spice library file name, pin mode. The spice file is parsed for interface configurations. Pins with pin select ([]) annotation are kept as individual pins using escaped identifiers. Normally standard cells reference library for cell mapping.
-v : input verilog file name
-o : output spice netlist file name
$1 : system var, which is filename1
$2 : system var, which is filename2

Commands to run LVS/DRC in console mode

calibre -lvs -hier lvs.runset

calibre -drc -hier drc.runset

To ignore a cell or region when running DRC/LVS

if a cell is not ready or a region where the design rule is violated, they can be ignored in the rule deck

     LAYOUT WINDEL 315 2638 384 2680 // ignore the rectangle region at (315, 2638) (384, 2680)

     EXCLUDE CELL "cell_name" // exclude the "cell_name"

     LVS BOX cell1 cell2 // treat cell1, cell2 as a black box, only check pin connection, not the inside netlist/layout of the cells. (useful for phantom cells or unfinished cells for doing LVS)

Layout pin text placement

The pin text on the layout can be specified by a text file rather than placing the text label on layout. This approach can be used for running LVS of a gds file which doesn't include any text information.         

LAYER M2_TXT 50 // define the layer        

TEXT LAYER M2_TXT // define layer as a text layer        

LAYOUT TEXT CLOCK 10.5 16.8 M2_TXT // place the text "CLOCK" at (10.5, 16.8) 

 the layout text can be included in a separated file to simplify the rule deck file