皮雅仕菲色陈: 2012

2012年11月14日星期三

function inside a struct

//---- test function inside struct
typedef struct try {
    void (*init)();
    void (*set)();
    void (*print)();
    int x,y;
} foo;

void init(foo *p)
{
    p->x=0;
    p->y=0;
}

void set(foo *p, int x, int y)
{
    p->x = x;
    p->y = y;
}

void print(foo *p)
{
    printf("x=%d, y=%d\n\r", p->x, p->y);
}

foo *initialize(void)
{
    foo *p   = (foo*)malloc(sizeof(foo));
    p->init = init;
    p->set   = set;
    p->print = print;

    return p;
}

//-------------------------------------
//----- test

foo *p = initialize();
p->init(p);
p->set(p, 10, 2);
p->print(p);
p->set(p, 15, 12);
p->print(p);

2012年10月24日星期三

JLink for Keil ARM

Use STM32F103T8 as an example:

Flash
--> Configure Flash Tool
    --> Utilities --> Use Target Driver for Flash Programming
           --> select "Cortex-M/R J-LINK/J-Trace
           --> Settings --> Programming Algorithm
           --> Add --> select "STM32F10X Med-density Flash" On-Chip Flash 128K

   --> Debug
          --> in Use, select "Cortex-M/R J-LINK/J-Trace"

2012年1月30日星期一

Layer mapping

Include the layer map file while stream-in a gds file from other libraries, the format are as below:

#Cadence layer name(by techfile) Cadence layer purpose Stream-in layer number(source) Stream-in data type
========================= ================= ========================= ===============
Nwell drawing 200 0
Poly drawing 204 0
Pisland drawing 202 0
Nisland drawing 201 0
Nselect drawing 205 0
Pselect drawing 206 0
Thickox drawing 203 0
Silblk drawing 207 0
Contact drawing 208 0
Met1 drawing 209 0
Via1 drawing 210 0
Met2 drawing 211 0
Via2 drawing 212 0
Met3 drawing 213 0
HR drawing 214 0
M1text text 226 0
M2text text 227 0
text drawing 21 0

the layers which did not specified in the layer map file will be ignored when stream-in.

To probe signal from layout for reviewing

This can be done by running DRC check
Keep the layer and connection definition, delete the rule checks in the rule deck (NOT the header file),
then add the following commands at end of the rule deck:

*** remember to set "DRC MAXIMUM RESULTS ALL", since the result output

*** may be exceed the max. limits

// probe nets
Plot_VDDA { @output all metal shapes belonging to VDDA net
NET Metaltop VDDA
NET Met3 VDDA
NET Met2 VDDA
NET PolyxRes VDDA
NET Nsd VDDA
NET Psd VDDA
}
DRC CHECK MAP Plot_VDDA GDSII 6 0 "./plots/VDDA.gds"

Convert verilog netlist to spice netlist

"v2lvs" (come along with Calibre) can convert verilog netlist to Calibre format netlist for LVS purpose

v2lvs -v verilog_in.v -o spice_out.sp -w 3

for more complex syntax put into a script, say "v2sp.sh"

v2lvs -n -s0 GND -s1 VDD -s inc_1.cdl -s inc_2.sp -lsp sp_ref_lib.sp -v $1 -o $2

e.g. run in console:
./v2sp.sh input.v output.sp

##
-n : make the unconnected pins to get numbered connections starting at 1000
-s0 : default global ground is changed to
-s1 : default global power is changed to
-s : causes the string .INCLUDE "filename" to be put at the beginning of the generated spice file
-lsp : Spice library file name, pin mode. The spice file is parsed for interface configurations. Pins with pin select ([]) annotation are kept as individual pins using escaped identifiers. Normally standard cells reference library for cell mapping.
-v : input verilog file name
-o : output spice netlist file name
$1 : system var, which is filename1
$2 : system var, which is filename2

Commands to run LVS/DRC in console mode

calibre -lvs -hier lvs.runset

calibre -drc -hier drc.runset

To ignore a cell or region when running DRC/LVS

if a cell is not ready or a region where the design rule is violated, they can be ignored in the rule deck

LAYOUT WINDEL 315 2638 384 2680 // ignore the rectangle region at (315, 2638) (384, 2680)

EXCLUDE CELL "cell_name" // exclude the "cell_name"

LVS BOX cell1 cell2 // treat cell1, cell2 as a black box, only check pin connection, not the inside netlist/layout of the cells. (useful for phantom cells or unfinished cells for doing LVS)

Layout pin text placement

The pin text on the layout can be specified by a text file rather than placing the text label on layout. This approach can be used for running LVS of a gds file which doesn't include any text information.

LAYER M2_TXT 50 // define the layer

TEXT LAYER M2_TXT // define layer as a text layer

LAYOUT TEXT CLOCK 10.5 16.8 M2_TXT // place the text "CLOCK" at (10.5, 16.8)

the layout text can be included in a separated file to simplify the rule deck file

Call an subcircuit when generating netlist in Analog Design Envirnment (ADE)

1) create a sch & symbol view for the subcircuit

2) copy the "symbo" view to "spectre" or "hspiceD", or others view as desired

3) open the base CDF for the cell, add a component partmer called "model" in the "Edit CDF Parameter" from, specify as belows:
paramType : String
parseAsNumber: no
parseAsCell : yes
storeDefault : no
name : model
prompt : Model Name
then press OK

4) in the "Simulation Information", edit the following parameters:
choose simulator : hspiceD, or others
otherParamters : model
instParameters : myParameters
componentName : (leave blank)
namePrefix : x
termOrder : the subcircuit terminals order

Finally, include the path of the subcircuit by hand edit in the generated netlist, or by
ADE --> Setup --> Model --> Model Libraries

Update:
Follow below steps yet works (without passing parameter) :-

repeat above point 1) & 2).
CDF : Simulatior Information
   |-- by simulator -> hspiceD
   |-- name prefix = x
   |-- termOrder = "a" "b" "c" etc. pin order same as subckt terminals

           Alt.
   |-- by simulator -> spectre
           |-- termOrde = "a" "b" "c" etc. pin order same as subck terminals

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